Date of Award

6-2020

Document Type

Union College Only

Degree Name

Bachelor of Science

Department

Computer Engineering

First Advisor

Cherrice Traver

Keywords

FPGA, ARM, Verilog, VHDL, Computer Vision, Image Processing

Abstract

Image processing can be a very inefficient task for traditional computers to compute. One way to improve the efficiency is to utilize Field Programmable Gate Arrays (FPGAs). These are programmable logic chips that allow for more parallelization than a traditional processor. The goal of our project was to implement an object detection algorithm using the communication between an FPGA and a traditional processor. We chose to work on the Histogram of Oriented Gradient (HOG) algorithm for the purpose of detecting stop signs in real time video. Our goal was to complete the gradient histogram generation on the FPGA and then pass the data to a traditional processor to detect the signs with a Support Vector Machine (SVM) with the histograms as features. Due to time constraints we were able to complete the first 3 steps in the algorithm, receiving video, detecting the edges, and calculating the gradients. We have also been able to transfer data from the FPGA to the processor, which is a large step toward hardware-software cohesion in our design.

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